Modern high-speed interconnect solutions are beginning to employ sophisticated data processing techniques to meet increasingly demanding performance requirements (e.g., high data bandwidth). When applied to memory systems, latency to an initial datum or idle latency is important as well as high data bandwidth. The employment of data processing techniques to improve bandwidth, however, can increase the idle latency of the memory system. A memory system typically has unique requirements that relate to the dynamic nature of its workload. For example, some memory systems have extended periods of idle time where the interconnect is unused. That idle time can allow the communications pipeline to empty. Restarting the communications pipeline and restarting the communication of useful data can take a relatively long time, depending upon the nature of the encoding/decoding algorithms used. After an idle period, the first datum in the communication pipeline typically is used to restart data processing, and the response time to this initial data is important to overall system performance. In this case, the bandwidth of the memory system may be less important than its idle latency (i.e., the amount of time from a memory request until a first datum is received by the requester). Similarly, once the communication pipeline is restarted and the memory system is storing or retrieving significant amounts of data, the idle latency of the memory system may be less important than its bandwidth.